1. Field of the Invention
The invention generally relates to on-chip data interfaces and in particular to integrated circuit chips having circuit units that may interchange requests and responses.
2. Description of the Related Art
Integrated circuit chips are often used for data processing and are known to comprise a number of different circuit units. Generally, each circuit unit is for performing a specific function, and of course there may be different circuit units provided on one chip for performing the same function or performing different functions. The circuit units may operate sequentially or simultaneously and they may function independently from each other or dependent on the operation of other circuit units.
In the latter case, the circuit units are usually interconnected via an interface to allow the circuit units to interchange data needed for making the operation of one circuit unit dependent on the operation of the other circuit unit. The data exchange is often done by sending transactions from one circuit unit to the other circuit unit. A transaction is a sequence of packets that are exchanged between the circuit units and that result in a transfer of information. The circuit unit initiating a transaction is called the source, and the circuit unit that ultimately services the transaction on behalf of the source is called the target. It is to be noted that there may also be intermediary units between the source and the target.
Transactions may be used to place a request or to respond to a received request. Taking the requests, posted requests may be distinguished from non-posted requests dependent on whether the request requires a response. Specifically, a non-posted request is a request that requires a response while a posted request does not require a response.
When focusing on the functions which are performed by the interconnected circuit units, the circuit units can often be divided into hosts and devices. The term host then means a circuit unit that provides services to the dependent device. A transaction from the host to the device is said to be downstream while a transaction in the other direction is said to be upstream. In bidirectional configurations, both the host and the device may send and receive requests and responses so that a device may be a source as well as a target, and the host may also function as a source as well as target.
A field where such integrated circuit chips are widely used are personal computers. Referring to FIG. 1, the hardware components of a common motherboard layout are depicted. It is to be noted that this figure shows only one example of a motherboard layout, and other configurations exist as well. The basic elements found on the motherboard of FIG. 1 include the CPU (Central Processing Unit) 100, a northbridge 105, a southbridge 110, and system memory 115. The northbridge 105 is usually a single chip in a core logic chip set that connects the processor 100 to the system memory 115 and, e.g., to the AGP (Accelerated Graphic Port) bus. Often a proprietary (or public) interface is provided between the processor 100 and northbridge 105 like, e.g. Athlon's proprietary FSB (Front Side Bus) EV6, the proprietary FSB (hublink) of Pentium 4, or Opteron's Hypertransport.
The southbridge 110 is usually the chip in a system core logic chip set that controls the IDE (Integrated Drive Electronics) or EIDE (Enhanced IDE) bus. The USB (Universal Serial Bus) that provides plug-n-play support manages the keyboard/mouse controller, provides power management features, and controls other peripherals. Common peripheral interfaces are, e.g. USB 2.0, EIDE, and SATA (Serial Advanced Technology Attachment).
FIG. 2 shows the components of a typical prior art southbridge. Of course, only a design example is illustrated in FIG. 2, and other arrangements exist as well. The device comprises a host circuit 210 and a device circuit 230. The host circuit 210 is connected by a chip-to-chip interface 200 to a northbridge or to another integrated circuit chip such as a memory controller or processor. On the other side, the southbridge includes a chip-to-peripheral interface 240 to connect the device circuit 230 to the peripherals. Further, there is an on-chip interface 220 provided between the host circuit 210 and the device circuit 230. This on-chip interface is usually a split transaction interface. Split transaction interfaces are interfaces where requests and responses are transferred on the bus as completely decoupled and independent transactions.
An example of a split transaction interface is shown in FIG. 3. Usually, a split transaction interface has two components: a target interface and a source interface. The target interface is the interface where requests (also denoted as “commands”) are sent downstream, i.e. from the host 300 to the device 345, and responses are sent upstream. On the other hand, the source interface is the interface where requests are sent upstream and responses downstream. For reasons of clarity, only the downstream parts of the interface are shown in FIG. 3.
In addition to the partitioning into the target and source interfaces, a split transaction interface is usually further split up into command interface units 305, 335 and response interface units 310, 340. While the command interface unit 305 of the host 300 is connected to the command interface unit 335 of the device 345 by multiple command signal lines 315, 320, the response interface unit 310 of the host 300 is connected to the response interface unit 340 of the device 345 by a number of response signal lines 325, 330. In particular, the command signal lines include a command transfer request signal line 315 over which the host 300 provides the device 345 with a command transfer request signal indicating that the host 300 is sending a command, and one or more command data signal lines 320 over which the data forming the command are sent. Accordingly, the response signal lines include a response transfer request signal line 325 and one or more response data signal lines 330.
While such a split transaction interface provides high speed data transport, this design suffers from the need for a large number of wires to implement the separated command interface units 305, 335 and response interface units 310, 340. Therefore, usual split transaction interfaces have the disadvantage of low design density and efficiency and thus increased manufacturing costs.